1. Technical Field
This disclosure relates generally to magnetic devices that utilize thin film fabrications on wafers, and more specifically, to methods for reducing defects in such fabrications that result from stresses in the films and warpage of the wafers during processing.
2. Description of the Related Art
Spin torque memory based, for example, on MTJ devices, is believed to be scalable down to characteristic technology dimensions on the order of 65 nm and even below. As the technology scales down, the budget for overlay design margins (i.e., room for error) will shrink correspondingly. Magnetic film depositions and annealing processes, for example those used in fabricating MTJ devices) normally introduce significant wafer warpage due to stresses in the films. Currently, most MRAM technology development is done on 200 mm wafers or smaller. When the technology is scaled down to 65 nm, the wafer warpage problem will be magnified because only the 300 mm wafer platform will be available. A further drawback of high stresses in the film depositions is the associated production of defects, such as film delaminations, which are already frequently encountered. The severity of such defects increases with the increases in annealing temperatures. There has been a recognition of the stress problem, as evidenced by U.S. Pat. No. 6,696,744 (Feygenson et al) and U.S. Patent Application 2010/0226042 (Nishimori et al). However, neither of these teachings provides a methodology for dealing with the problem in the manner of the present disclosure.
The following brief and schematic description of a current process to form and process thin-film layered structures will indicate the difficulties encountered. It is these difficulties that will be addressed using the methods of the present disclosure.
Exemplary Current Process
Schematic FIG. 6a, illustrates a first step in an exemplary current process. Its corresponding first process step is described briefly in the first box (1) of the process flow chart of FIG. 2. FIG. 6a (and box (1) of FIG. 2) shows, schematically, in cross-section, a “last metal layer” (50) of a CMOS substrate (full substrate not shown) that will have an MTJ multi-layered deposition (not yet shown) formed over its upper surface and thereby be connected to the CMOS devices and associated circuitry within the substrate. It is to be noted that in this and in all the following descriptions we use the phrase “last metal layer” to refer to an uppermost layer of a CMOS substrate. This last layer contains the metal, electrically conductive connections that will be made to multi-layer thin-film depositions that will be deposited on this last layer of the substrate. When we refer more generally to a CMOS substrate, we mean a substrate that contains within its body CMOS circuitry that would be used to activate the thin-film, multi-layered MTJ devices (formed on its “last metal layer”) such as those in an MRAM array. However, it should also be pointed out that the general approach described herein to forming a thin-film multi-layered deposition that will not be subject to defects resulting from process-induced stresses could apply equally well to other wafer-sized substrates that incur warpage when subjected to thermal processes and to other thin film depositions of sufficient size to experience stresses and stress-related defects when formed on such substrates.
The CMOS last metal layer (50) is the uppermost layer of the CMOS substrate (not shown) and it will be assumed to be the starting layer for subsequent process steps in all the methods described herein. It is also assumed, for simplicity, that the CMOS last metal layer includes a segmented, electrically conductive (e.g. metal) connection layer (70) within its upper surface, surrounded by structurally supportive and insulating dielectric material (75), and that the connection layer (70) will ultimately contact appropriate portions of the about-to-be-fabricated MTJ deposition through an interconnecting layer called (in block (2) of FIG. 2) a “connection via & interface layer”. It is further assumed that these same conducting connection layers (70) lead to CMOS circuit elements in the CMOS substrate that is beneath the last metal layer. These connections will not be shown herein, however, and the last metal layer will serve to represent all CMOS circuitry in the substrate.
Referring next to the illustration of FIG. 6b and to the description in the second process step of block (2) in FIG. 2, there is illustrated and described a second current process step in the fabrication of an MTJ layer, which is to build a connection via and interface layer which will serve to connect the subsequent MTJ fabrication to the last metal layer ((50) of FIG. 6a) and, thereupon, to the CMOS circuitry. A conducting via (80) is shown above each connecting layer segment (70), each via passing through a first dielectric layer (90), which is an etch-stop layer, and a second dielectric layer (95), which is an interface layer, and terminating at a junction connection (105) that will ultimately contact appropriate portions of an MTJ thin-film deposition. The structure now completed on the last metal layer, including elements (90), (80), (95) and (105) is the “connection via & interface layer” described in bock (2) of FIG. 2. A detailed description of the mode of fabrication of this layer will not be described herein, but new forms of this layer will be described in detail below.
Referring now to FIG. 6c and to the remaining process sequence in FIG. 2, process boxes (3) and (4), describe, sequentially, the formation of an alignment layer (the zero-layer) and a continuous MTJ film deposition on the fabrication of FIG. 6b. In FIG. 6c, the alignment layer and the MTJ film are indicated as a single layer (120), which would typically be formed as two separate but contiguous layers.
Referring finally to FIG. 2, process steps of blocks (5)-(7), there is described a series of exemplary processes performed on the alignment layer and MTJ film (120), including, for example, an anneal, a photo-patterning (e.g. deposition of a photo-resist layer or equivalent photo-lithographic emulsion) and a subsequent etch. It is these subsequent processes that, in the current practice, will be associated with wafer warpage and defects in the MTJ film (120). In the processes to be described below, methods for eliminating these defects will be described.